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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74ALVCH16501DL

18-bit universal bus transceiver; 3-state

The 74ALVCH16501 is an 18-bit universal transceiver with bus hold inputs and 3-state outputs. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH and OEBA is active LOW). This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

此產品已停產

Features and benefits

  • Wide supply voltage range from 1.2 V to 3.6 V

  • CMOS low power dissipation

  • Direct interface with TTL levels

  • Current drive ±24 mA at VCC = 3.0 V

  • Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched or clocked mode

  • Bus hold on all data inputs

  • Output drive capability 50 Ω transmission lines at 85 °C

  • 3-state non-inverting outputs for bus-oriented applications

  • Latch-up performance exceeds 100 mA per JESD78 Class II.A

  • Complies with JEDEC standards:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C

參數類型

型號 Package name
74ALVCH16501DL SSOP56

封裝

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號，（訂購碼(12NC)） 狀態 標示 封裝 外形圖 回流焊/波峰焊 包裝
74ALVCH16501DL 74ALVCH16501DL,112
(935263882112)		 Obsolete ALVCH16501 Standard Procedure Standard Procedure SOT371-1
SSOP56
(SOT371-1) 		SOT371-1 SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE
暫無信息
74ALVCH16501DL,118
(935263882118)		 Obsolete ALVCH16501 Standard Procedure Standard Procedure 暫無信息

環境信息

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74ALVCH16501DL 74ALVCH16501DL,112 74ALVCH16501DL rohs rhf rhf
74ALVCH16501DL 74ALVCH16501DL,118 74ALVCH16501DL rohs rhf rhf
品質及可靠性免責聲明

文檔 (6)

文件名稱 標題 類型 日期
74ALVCH16501 18-bit universal bus transceiver; 3-state Data sheet 2024-07-01
alvch16501 alvch16501 IBIS model IBIS model 2013-04-08
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT371-1 plastic, shrink small outline package; 56 leads; 0.635 mm pitch; 18.45 mm x 7.5 mm x 2.8 mm body Package information 2020-04-21
SSOP-TSSOP-VSO-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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模型

文件名稱 標題 類型 日期
alvch16501 alvch16501 IBIS model IBIS model 2013-04-08

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.