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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74ALVT16823DL

18-bit bus-interface D-type flip-flop with reset and enable; 3?-?state

The 74ALVT16823 is an 18??-??bit positive?-?edge triggered D?-?type flip?-?flop with 3?-?state outputs, reset and enable.

The device can be used as two 9?-?bit flip?-?flops or one 18?-?bit flip?-?flop. The device features clock (nCP), clock enable (nCE), master reset (nMR) and output enable (nOE, inputs each controlling 9?-?bits. When nCE is LOW, the flip?-?flops will store the state of their individual D?-?inputs that meet the set?-?up and hold time requirements on the LOW?-?to?-?HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high?-?impedance OFF?-?state. Operation of the nOE input does not affect the state of the flip?-?flops. A LOW on nMR will reset the flip?-?flops LOW. Bus hold data inputs eliminate the need for external pull?-?up resistors to define unused inputs

此產品已停產

Features and benefits

  • Wide supply voltage range from 2.3 V to 3.6 V

  • Overvoltage tolerant inputs to 5.5 V

  • BiCMOS high speed and output drive

  • Direct interface with TTL levels

  • Bus hold on data inputs

  • Power-up 3-state

  • IOFF circuitry provides partial Power-down mode operation

  • Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops

  • Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors

  • Live insertion and extraction permitted

  • Power-up reset

  • No bus current loading when output is tied to 5 V bus

  • Output capability: +64 mA to -32 mA

  • Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to 85 °C

參數類型

型號 Package name
74ALVT16823DL SSOP56

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號，（訂購碼(12NC)） 狀態 標示 封裝 外形圖 回流焊/波峰焊 包裝
74ALVT16823DL 74ALVT16823DL,112
(935261020112)		 Obsolete ALVT16823 SOT371-1
SSOP56
(SOT371-1) 		SOT371-1 SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE
暫無信息
74ALVT16823DL,118
(935261020118)		 Obsolete ALVT16823 暫無信息
74ALVT16823DL,512
(935261020512)		 Obsolete ALVT16823 暫無信息
74ALVT16823DL,518
(935261020518)		 Obsolete ALVT16823 暫無信息

環境信息

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74ALVT16823DL 74ALVT16823DL,112 74ALVT16823DL rhf
74ALVT16823DL 74ALVT16823DL,118 74ALVT16823DL rhf
74ALVT16823DL 74ALVT16823DL,512 74ALVT16823DL rohs rhf rhf
74ALVT16823DL 74ALVT16823DL,518 74ALVT16823DL rohs rhf rhf
品質及可靠性免責聲明

文檔 (7)

文件名稱 標題 類型 日期
74ALVT16823 18-bit bus-interface D-type flip-flop with reset and enable; 3?-?state Data sheet 2024-06-25
alvt16823 alvt16823 IBIS model IBIS model 2013-04-08
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT371-1 plastic, shrink small outline package; 56 leads; 0.635 mm pitch; 18.45 mm x 7.5 mm x 2.8 mm body Package information 2020-04-21
SSOP-TSSOP-VSO-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
alvt16 alvt16 Spice model SPICE model 2013-05-07
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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模型

文件名稱 標題 類型 日期
alvt16823 alvt16823 IBIS model IBIS model 2013-04-08
alvt16 alvt16 Spice model SPICE model 2013-05-07

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.