可訂購部件
| 型號(hào) | 可訂購的器件編號(hào) | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74AUP1G175GW | 74AUP1G175GW,125 | 935280003125 | SOT363-2 | 訂單產(chǎn)品 |
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Click here for more information74AUP1G175GW
Low-power D-type flip-flop with reset; positive-edge trigger
The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be reset to LOW. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Alternatives
Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
CMOS low power dissipation
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
Low static power consumption; ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|
| 74AUP1G175GW | 0.8?-?3.6 | CMOS | ± 1.9 | 7.4 | 70 | ultra low | -40~125 | TSSOP6 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
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封裝
| 型號(hào) | 可訂購的器件編號(hào)，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AUP1G175GW | 74AUP1G175GW,125 (935280003125) |
Active | aT |
TSSOP6 (SOT363-2) |
SOT363-2 | SOT363-2_125 |
環(huán)境信息
| 型號(hào) | 可訂購的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AUP1G175GW | 74AUP1G175GW,125 | 74AUP1G175GW |
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Series
文檔 (9)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74AUP1G175 | Low-power D-type flip-flop with reset; positive-edge trigger | Data sheet | 2023-07-13 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11052 | Pin FMEA for AUP family | Application note | 2019-01-09 |
| SOT363-2 | 3D model for products with SOT363-2 package | Design support | 2023-02-02 |
| aup1g175 | aup1g175 IBIS model | IBIS model | 2014-12-21 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
| SOT363-2 | plastic thin shrink small outline package; 6 leads; body width 1.25 mm | Package information | 2022-11-21 |
| SOT363-2_125 | TSSOP6 ; Reel pack for SMD, 7"; Q3/T4 product orientation | Packing information | 2022-11-04 |
| 74AUP1G175GW_Nexperia_Product_Reliability | 74AUP1G175GW Nexperia Product Reliability | Quality document | 2024-06-16 |
支持
如果您需要設(shè)計(jì)/技術(shù)支持，請告知我們并填寫 應(yīng)答表 我們會(huì)盡快回復(fù)您。
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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訂購、定價(jià)與供貨
| 型號(hào) | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74AUP1G175GW | 74AUP1G175GW,125 | 935280003125 | Active | SOT363-2_125 | 3,000 | 訂單產(chǎn)品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74AUP1G175GW
Low-power D-type flip-flop with reset; positive-edge trigger
從安世半導(dǎo)體購買
| SKU | 庫存* | MOQ | 單位價(jià)格 | 數(shù)量 |
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