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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74AUP2G240GF

Low-power dual inverting buffer/line driver; 3-state

The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE causes the output to assume a high-impedance OFF-state.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input nOE is HIGH.

此產品已停產

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V

  • High noise immunity

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • Low static power consumption; ICC = 0.9 μA (maximum)

  • Latch-up performance exceeds 100 mA per JESD78 Class II

  • Inputs accept voltages up to 3.6 V

  • Low-noise overshoot and undershoot < 10 % of VCC

  • Input-disable feature allows floating input conditions

  • IOFF circuitry provides partial Power-down mode operation

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

參數類型

型號 Package name
74AUP2G240GF XSON8

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號，（訂購碼(12NC)） 狀態 標示 封裝 外形圖 回流焊/波峰焊 包裝
74AUP2G240GF 74AUP2G240GF,115
(935291479115)		 Obsolete p2 SOT1089
XSON8
(SOT1089) 		SOT1089 REFLOW_BG-BD-1
SOT1089_115

環境信息

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74AUP2G240GF 74AUP2G240GF,115 74AUP2G240GF rohs rhf rhf
品質及可靠性免責聲明

文檔 (11)

文件名稱 標題 類型 日期
74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Data sheet 2023-07-27
AN11052 Pin FMEA for AUP family Application note 2019-01-09
Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
SOT1089 3D model for products with SOT1089 package Design support 2019-10-07
aup2g240 aup2g240 IBIS model IBIS model 2013-04-07
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Leaflet 2019-04-12
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
XSON8_SOT1089_mk plastic, extremely thin small outline package; no leads; 8 terminals; 0.55 mm pitch; 1.35 mm x 1 mm x 0.5 mm body Marcom graphics 2017-01-28
SOT1089 plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.5 mm body Package information 2022-06-03
REFLOW_BG-BD-1 Reflow soldering profile Reflow soldering 2021-04-06
MAR_SOT1089 MAR_SOT1089 Topmark Top marking 2013-06-03

支持

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模型

文件名稱 標題 類型 日期
aup2g240 aup2g240 IBIS model IBIS model 2013-04-07
SOT1089 3D model for products with SOT1089 package Design support 2019-10-07

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.