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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74AUP3G0434GT

Low-power dual inverter and single buffer

The 74AUP3G0434 is a dual inverter and single buffer.

Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V

  • High noise immunity

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • Low static power consumption; ICC = 0.9 μA (maximum)

  • Latch-up performance exceeds 100 mA per JESD 78B Class II

  • Inputs accept voltages up to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial Power-down mode operation

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

參數類型

型號 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AUP3G0434GT 0.8?-?3.6 CMOS ± 1.9 4.0 70 3 ultra low -40~125 XSON8

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態 標示 封裝 外形圖 回流焊/波峰焊 包裝
74AUP3G0434GT 74AUP3G0434GTX
(935299445115)
Active pZ SOT833-1
XSON8
(SOT833-1)
SOT833-1 SOT833-1_115

環境信息

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74AUP3G0434GT 74AUP3G0434GTX 74AUP3G0434GT rohs rhf rhf
品質及可靠性免責聲明

文檔 (11)

文件名稱 標題 類型 日期
74AUP3G0434 Low-power dual inverter and single buffer Data sheet 2024-04-26
Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
SOT833-1 3D model for products with SOT833-1 package Design support 2021-01-28
aup3g0434 IBIS model IBIS model 2014-06-04
Nexperia_document_Logic_CombinationLogic_infocard_201710 Combination logic solutions card Leaflet 2019-08-09
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Leaflet 2019-04-12
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT833-1 plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm body Package information 2022-06-03
SOT833-1_115 XSON8; Reel pack for SMD, 7''; Q1/T1 product orientation Packing information 2020-04-21
74AUP3G0434GT_Nexperia_Product_Reliability 74AUP3G0434GT Nexperia Product Reliability Quality document 2024-06-16
MAR_SOT833 MAR_SOT833 Topmark Top marking 2013-06-03

支持

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模型

文件名稱 標題 類型 日期
aup3g0434 IBIS model IBIS model 2014-06-04
SOT833-1 3D model for products with SOT833-1 package Design support 2021-01-28

PCB Symbol, Footprint and 3D Model

Model Name 描述

訂購、定價與供貨

型號 Orderable part number Ordering code (12NC) 狀態 包裝 Packing Quantity 在線購買
74AUP3G0434GT 74AUP3G0434GTX 935299445115 Active SOT833-1_115 5,000 訂單產品

樣品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購部件

型號 可訂購的器件編號 訂購代碼(12NC) 封裝 從經銷商處購買
74AUP3G0434GT 74AUP3G0434GTX 935299445115 SOT833-1 訂單產品