74AVC4T3144GU12-Q100

4-bit dual-supply buffer/level translator; 3-state

Automotive qualified

The 74AVC4T3144-Q100 is a 4-bit, dual-supply level translating buffer with 3-state outputs. It features four data inputs (An and B4), four data outputs (YBn and YA4), and an output enable input (OE). The device is configured to translate three inputs from V_CC(A) to V_CC(B) and one input from V_CC(B) to V_CC(A). OE, An and YA4 are referenced to V_CC(A) and YBn and B4 are referenced to V_CC(B). A HIGH on OE causes the outputs to assume a high-impedance OFF-state.

The device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables outputs, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V_CC(A) or V_CC(B) are at GND level, all outputs are in the high?-?impedance OFF-state.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range:
- V_CC(A): 0.8 V to 3.6 V
- V_CC(B): 0.8 V to 3.6 V
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
Maximum data rates:
- 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
- 200 Mbit/s (≥ 1.1 V to 3.3 V translation)
- 200 Mbit/s (≥ 1.1 V to 2.5 V translation)
- 200 Mbit/s (≥ 1.1 V to 1.8 V translation)
- 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
- 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
I_OFF circuitry provides partial Power-down mode operation
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3B exceeds 8000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

參數類型

型號	V_CC (V)	Logic switching levels	Output drive capability (mA)	Nr of bits	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AVC4T3144GU12-Q100	n.a.	CMOS/LVTTL	± 12	4	very low	-40~125	188	6.2	96	XQFN12

封裝

型號	可訂購的器件編號，（訂購碼(12NC)）	狀態	標示	封裝	外形圖	回流焊/波峰焊	包裝
74AVC4T3144GU12-Q100	74AVC4T3144GU12-QX (935690912115)	Active		XQFN12 (SOT1174-1)	SOT1174-1		SOT1174-1_115

環境信息

型號	可訂購的器件編號	化學成分	RoHS	RHF指示符
74AVC4T3144GU12-Q100	74AVC4T3144GU12-QX	74AVC4T3144GU12-Q100

品質及可靠性免責聲明

Series

文檔 (9)

文件名稱	標題	類型	日期
74AVC4T3144_Q100	4-bit dual-supply buffer/level translator; 3-state	Data sheet	2024-07-02
AN90007	Pin FMEA for AVC family	Application note	2018-11-30
SOT1174-1	3D model for products with SOT1174-1 package	Design support	2021-01-28
avc4t3144	IBIS model of 74AVC4T3144	IBIS model	2017-12-22
74AVC4T3144_and_74LVC4T3144_leaflet	Dual supply translating buffers/line drivers	Leaflet	2018-03-09
Nexperia_package_poster	Nexperia package poster	Leaflet	2020-05-15
SOT1174-1	plastic, leadless extremely thin quad flat package; 12 terminals; 0.4 mm pitch; 2 mm x 1.7 mm x 0.5 mm body	Package information	2024-04-11
SOT1174-1_115	XQFN12; Reel pack for SMD, 7''; Q1/T1 product orientation	Packing information	2020-04-21
74AVC4T3144GU12-Q100_Nexperia_Product_Reliability	74AVC4T3144GU12-Q100 Nexperia Product Reliability	Quality document	2024-06-16

支持

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模型

文件名稱	標題	類型	日期
avc4t3144	IBIS model of 74AVC4T3144	IBIS model	2017-12-22
SOT1174-1	3D model for products with SOT1174-1 package	Design support	2021-01-28

訂購、定價與供貨

型號	Orderable part number	Ordering code (12NC)	狀態	包裝	Packing Quantity	在線購買
74AVC4T3144GU12-Q100	74AVC4T3144GU12-QX	935690912115	Active	SOT1174-1_115	4,000	訂單產品

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