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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調(diào)節(jié)ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產(chǎn)品(AEC-Q100/Q101)

74AXP1T32GX

Dual supply 2-input OR gate

The 74AXP1T32 is a dual supply 2-input OR gate. It features two inputs (A, B), an output (Y) and dual supply pins (VCCI and VCCO). The inputs are referenced to VCCI and the output is referenced to VCCO. All inputs can be connected directly to VCCI or GND. VCCI can be supplied at any voltage between 0.7 V and 2.75 V. VCCO can be supplied at any voltage between 1.2 V and 5.5 V. This feature allows voltage level translation.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire supply range and is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

此產(chǎn)品已停產(chǎn)

Features and benefits

  • Wide supply voltage range:

    • VCCI: 0.7 V to 2.75 V

    • VCCO: 1.2 V to 5.5 V

  • Low input capacitance; CI = 0.6 pF (typical)

  • Low output capacitance; CO = 1.8 pF (typical)

  • Low dynamic power consumption; CPD = 0.5 pF at VCCI = 1.2 V (typical)

  • Low dynamic power consumption; CPD = 7.1 pF at VCCO = 3.3 V (typical)

  • Low static power consumption; ICCI = 0.5 μA (85 °C maximum)

  • Low static power consumption; ICCO = 1.8 μA (85 °C maximum)

  • High noise immunity

  • Complies with JEDEC standard:

    • JESD8-12A.01 (1.1 V to 1.3 V; A, B input)

    • JESD8-11A.01 (1.4 V to 1.6 V)

    • JESD8-7A (1.65 V to 1.95 V)

    • JESD8-5A.01 (2.3 V to 2.7 V)

    • JESD8-C (2.7 V to 3.6 V; Y output)

    • JESD12-6 (4.5 V to 5.5 V; Y output)

  • ESD protection:

    • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV

    • CDM JESD22-C101E exceeds 1000 V

  • Latch-up performance exceeds 100 mA per JESD78D Class II

  • Inputs accept voltages up to 2.75 V

  • Low noise overshoot and undershoot < 10 % of VCCO

  • IOFF circuitry provides partial power-down mode operation

  • Multiple package options

  • Specified from -40 °C to +85 °C

參數(shù)類型

型號 Logic switching levels Output drive capability (mA) tpd (ns) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AXP1T32GX CMOS ± 12 4.6 1 ultra low -40~85 X2SON6

封裝

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號，（訂購碼(12NC)） 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74AXP1T32GX 74AXP1T32GXZ
(935308977147)		 Withdrawn / End-of-life rT SOT1255-2
X2SON6
(SOT1255-2) 		SOT1255-2 SOT1255-2_147

環(huán)境信息

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74AXP1T32GX 74AXP1T32GXZ 74AXP1T32GX rohs rhf rhf
品質(zhì)及可靠性免責聲明

文檔 (9)

文件名稱 標題 類型 日期
74AXP1T32 Dual supply 2-input OR gate Data sheet 2022-02-28
AN90029 Pin FMEA for AXPnT family Application note 2021-07-13
Nexperia_document_guide_Logic_translators Nexperia Logic Translators Brochure 2021-04-12
SOT1255-2 3D model for products with SOT1255-2 package Design support 2021-01-28
axp1t32 74AXP1T32 IBIS Model IBIS model 2016-12-12
Nexperia_document_leaflet_Logic_AXP_technology_portfolio_201904 AXP – Extremely low-power logic technology portfolio Leaflet 2019-04-05
Nexperia_document_leaflet_Logic_X2SON_packages_062018 X2SON ultra-small 4, 5, 6 & 8-pin leadless packages Leaflet 2018-06-05
SOT1255-2 plastic thermal enhanced extremely thin small outline package; no leads;6 terminals; body 1.0 x 0.8 x 0.32 mm Package information 2020-08-27
74AXP1T32GX_Nexperia_Product_Reliability 74AXP1T32GX Nexperia Product Reliability Quality document 2022-05-04

支持

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模型

文件名稱 標題 類型 日期
axp1t32 74AXP1T32 IBIS Model IBIS model 2016-12-12
SOT1255-2 3D model for products with SOT1255-2 package Design support 2021-01-28

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.