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Click here for more information74HC00DB
Quad 2-input NAND gate
The 74HC00; 74HCT00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Alternatives
Features and benefits
Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Input levels:
For 74HC00: CMOS level
For 74HCT00: TTL level
Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
- ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
PCB Symbol, Footprint and 3D Model
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封裝
下表中的所有產品型號均已停產 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態 | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74HC00DB | 74HC00DB,112 (935174120112) |
Obsolete | no package information | ||||
| 74HC00DB,118 (935174120118) |
Obsolete | ||||||
環境信息
下表中的所有產品型號均已停產 。
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74HC00DB | 74HC00DB,112 | 74HC00DB |
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| 74HC00DB | 74HC00DB,118 | 74HC00DB |
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Series
文檔 (4)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74HC_HCT00 | Quad 2-input NAND gate | Data sheet | 2024-02-15 |
| AN11044 | Pin FMEA 74HC/74HCT family | Application note | 2019-01-09 |
| hc | HC/HCT Spice model | SPICE model | 2022-02-17 |
| HCT_USER_GUIDE | HC/T User Guide | User manual | 1997-10-31 |
支持
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模型
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| hc | HC/HCT Spice model | SPICE model | 2022-02-17 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.