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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74LV7032APW-Q100

Quad 2-input OR gate with Schmitt trigger inputs

The 74LV7032A-Q100 is a quad 2-input OR function with Schmitt-trigger inputs, capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Wide supply voltage range from 2.0 V to 5.5 V

  • Maximum tpd of 9.5 ns at 5 V

  • Typical VOL(p) < 0.8 V at VCC = 3.3 V, Tamb = 25 °C

  • Typical VOH(v) > 2.3 V at VCC = 3.3 V, Tamb = 25 °C

  • Supports mixed-mode voltage operation on all ports

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 250 mA per JESD 78 Class II

  • ESD protection:

  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

  • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

參數類型

型號 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Ψth(j-top) (K/W) Rth(j-c) (K/W) Package name
74LV7032APW-Q100 2.0?-?5.5 CMOS ± 12 4.3 45 4 low -40~125 140 7.5 66 TSSOP14

封裝

型號 可訂購的器件編號，（訂購碼(12NC)） 狀態 標示 封裝 外形圖 回流焊/波峰焊 包裝
74LV7032APW-Q100 74LV7032APW-Q100J
(935691318118)		 Active LV7032A SOT402-1
TSSOP14
(SOT402-1) 		SOT402-1 SSOP-TSSOP-VSO-WAVE
SOT402-1_118

環境信息

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74LV7032APW-Q100 74LV7032APW-Q100J 74LV7032APW-Q100 rohs rhf rhf
品質及可靠性免責聲明

文檔 (8)

文件名稱 標題 類型 日期
74LV7032A_Q100 Quad 2-input OR gate with Schmitt trigger inputs Data sheet 2024-04-08
SOT402-1 3D model for products with SOT402-1 package Design support 2023-02-02
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
TSSOP14_SOT402-1_mk plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body Marcom graphics 2017-01-28
SOT402-1 plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body Package information 2023-11-07
SOT402-1_118 TSSOP14; Reel pack for SMD, 13"; Q1/T1 product orientation Packing information 2020-04-21
74LV7032APW-Q100_Nexperia_Product_Reliability 74LV7032APW-Q100 Nexperia Product Reliability Quality document 2024-06-16
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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模型

文件名稱 標題 類型 日期
SOT402-1 3D model for products with SOT402-1 package Design support 2023-02-02

訂購、定價與供貨

型號 Orderable part number Ordering code (12NC) 狀態 包裝 Packing Quantity 在線購買
74LV7032APW-Q100 74LV7032APW-Q100J 935691318118 Active SOT402-1_118 2,500 訂單產品

樣品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購部件

型號 可訂購的器件編號 訂購代碼(12NC) 封裝 從經銷商處購買
74LV7032APW-Q100 74LV7032APW-Q100J 935691318118 SOT402-1 訂單產品