可訂購部件
型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經銷商處購買 |
---|---|---|---|---|
74LVC1G80GV | 74LVC1G80GV,125 | 935272023125 | SOT753 | 訂單產品 |
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Click here for more informationSingle D-type flip-flop; positive-edge trigger
The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
±24 mA output drive (VCC = 3.0 V)
CMOS low power dissipation
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C.
型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
---|---|---|---|---|---|---|---|---|---|---|---|
74LVC1G80GV | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 2.4 | 450 | low | -40~125 | 270 | 63.3 | 169 | TSOP5 |
Model Name | 描述 |
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型號 | 可訂購的器件編號,(訂購碼(12NC)) | 狀態 | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
---|---|---|---|---|---|---|---|
74LVC1G80GV | 74LVC1G80GV,125 (935272023125) |
Active | V80 |
TSOP5 (SOT753) |
SOT753 |
REFLOW_BG-BD-1
WAVE_BG-BD-1 |
SOT753_125 |
文件名稱 | 標題 | 類型 | 日期 |
---|---|---|---|
74LVC1G80 | Single D-type flip-flop; positive-edge trigger | Data sheet | 2024-11-12 |
AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
SOT753 | 3D model for products with SOT753 package | Design support | 2019-01-22 |
lvc1g80 | 74LVC1G80 IBIS model | IBIS model | 2014-10-20 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
SOT753 | plastic, surface-mounted package; 5 leads; 0.95 mm pitch; 2.9 mm x 1.5 mm x 1 mm body | Package information | 2022-05-31 |
SOT753_125 | TSOP5; Reel pack for SMD, 7"; Q3/T4 product orientation | Packing information | 2020-04-21 |
74LVC1G80GV_Nexperia_Product_Reliability | 74LVC1G80GV Nexperia Product Reliability | Quality document | 2024-06-16 |
REFLOW_BG-BD-1 | Reflow soldering profile | Reflow soldering | 2021-04-06 |
lvc | lvc Spice model | SPICE model | 2013-05-07 |
MAR_SOT753 | MAR_SOT753 Topmark | Top marking | 2013-06-03 |
WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
型號 | Orderable part number | Ordering code (12NC) | 狀態 | 包裝 | Packing Quantity | 在線購買 |
---|---|---|---|---|---|---|
74LVC1G80GV | 74LVC1G80GV,125 | 935272023125 | Active | SOT753_125 | 3,000 | 訂單產品 |
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The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.