可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經銷商處購買 |
|---|---|---|---|---|
| 74LVC273BQ | 74LVC273BQ,115 | 935273677115 | SOT764-1 | 訂單產品 |
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Click here for more information74LVC273BQ
Octal D-type flip-flop with reset; positive-edge trigger
The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
Alternatives
Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Overvoltage tolerant inputs to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Output drive capability 50 Ω transmission lines at +85 °C
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|
| 74LVC273BQ | 1.2?-?3.6 | CMOS/LVTTL | ± 24 | 6.0 | 230 | low | -40~125 | DHVQFN20 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態 | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC273BQ | 74LVC273BQ,115 (935273677115) |
Active | LVC273 |
DHVQFN20 (SOT764-1) |
SOT764-1 | SOT764-1_115 |
文檔 (11)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC273 | Octal D-type flip-flop with reset; positive-edge trigger | Data sheet | 2023-08-25 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN263 | Power considerations when using CMOS and BiCMOS logic devices | Application note | 2023-02-07 |
| SOT764-1 | 3D model for products with SOT764-1 package | Design support | 2019-10-03 |
| lvc273 | lvc273 IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| DHVQFN20_SOT764-1_mk | plastic, dual in-line compatible thermal enhanced very thin quad flat package; 20 terminals; 0.5 mm pitch; 2.5 mm x 4.5 mm x 0.85 mm body | Marcom graphics | 2017-01-28 |
| SOT764-1 | plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 20 terminals; 0.5 mm pitch; 4.5 mm x 2.5 mm x 1 mm body | Package information | 2022-06-21 |
| SOT764-1_115 | DHVQFN20; Reel pack for SMD, 7''; Q1/T1 product orientation | Packing information | 2020-04-21 |
| 74LVC273BQ_Nexperia_Product_Reliability | 74LVC273BQ Nexperia Product Reliability | Quality document | 2024-06-16 |
| lvc | lvc Spice model | SPICE model | 2013-05-07 |
訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態 | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74LVC273BQ | 74LVC273BQ,115 | 935273677115 | Active | SOT764-1_115 | 3,000 | 訂單產品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74LVC273BQ
Octal D-type flip-flop with reset; positive-edge trigger
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