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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節(jié)ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74LVC823ABQ-Q100

9-bit D-type flip-flop with 5 V tolerant inputs?/?outputs; positive?edge?-?trigger; 3?-?state

The 74LVC823A-Q100 is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip?-?flops stores the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition, provided pin CE is LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all flip-flops. When pin OE is LOW, the contents of the 9 flip?-?flops are available at the outputs. When pin OE is HIGH, the outputs go to the high?-?impedance OFF?-?state. Operation of the OE input does not affect the state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V applications.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

此產品已停產

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • 5 V tolerant inputs/outputs for interfacing with 5 V logic
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power consumption
  • Direct interface with TTL levels
  • Flow-through pinout architecture
  • 9-bit positive edge-triggered register
  • Independent register and 3-state buffer operation
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • MIL-STD-883, method 3015 exceeds 2000 V
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
  • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints

封裝

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74LVC823ABQ-Q100 74LVC823ABQ-Q100J
(935332776118)
Obsolete no package information

環(huán)境信息

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74LVC823ABQ-Q100 74LVC823ABQ-Q100J 74LVC823ABQ-Q100 rohs rhf rhf
品質及可靠性免責聲明

文檔 (5)

文件名稱 標題 類型 日期
74LVC823A_Q100 9-bit D-type flip-flop with 5 V tolerant inputs?/?outputs; positive?edge?-?trigger; 3?-?state Data sheet 2020-06-19
AN11009 Pin FMEA for LVC family Application note 2019-01-09
AN263 Power considerations when using CMOS and BiCMOS logic devices Application note 2023-02-07
lvc823a lvc823a IBIS model IBIS model 2013-04-09
lvc lvc Spice model SPICE model 2013-05-07

支持

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模型

文件名稱 標題 類型 日期
lvc823a lvc823a IBIS model IBIS model 2013-04-09
lvc lvc Spice model SPICE model 2013-05-07

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.