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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調(diào)節(jié)ESD保護

MOSFET

氮化鎵場效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認證產(chǎn)品(AEC-Q100/Q101)

74LVCH16245AEV

16-bit bus transceiver with direction pin; 5 V tolerant; 3-state

The 74LVC16245A; 74LVCH16245A is a 16-bit transceiver with 3-state outputs. The device can be used as two 8-bit transceivers or one 16-bit transceiver. The device features two output enables (1OE and 2OE) each controlling eight outputs, and two send/receive (1DIR and 2DIR) inputs for direction control. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

The 74LVCH16245A bus hold on data inputs eliminates the need for external pull?-?up resistors to hold unused inputs.

此產(chǎn)品已停產(chǎn)

Features and benefits

  • Overvoltage tolerant inputs to 5.5 V

  • Wide supply voltage range from 1.2 V to 3.6 V

  • CMOS low power dissipation

  • MULTIBYTE flow-through standard pin-out architecture

  • Low inductance multiple power and ground pins for minimum noise and ground bounce

  • Direct interface with TTL levels

  • IOFF circuitry provides partial Power-down mode operation

  • All data inputs have bus hold (74LVCH16245A only)

  • Complies with JEDEC standard:

    • JESD8-7A (1.65 V to 1.95 V)

    • JESD8-5A (2.3 V to 2.7 V)

    • JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

參數(shù)類型

型號 Package name
74LVCH16245AEV VFBGA56

封裝

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74LVCH16245AEV 74LVCH16245AEV,118
(935271944118)
Obsolete LVCH16245A Standard Procedure Standard Procedure no package information
74LVCH16245AEV,151
(935271944151)
Obsolete LVCH16245A Standard Procedure Standard Procedure
74LVCH16245AEV,157
(935271944157)
Obsolete LVCH16245A Standard Procedure Standard Procedure
74LVCH16245AEVY
(935271944518)
Obsolete LVCH16245A Standard Procedure Standard Procedure
74LVCH16245AEV,551
(935271944551)
Obsolete LVCH16245A Standard Procedure Standard Procedure
74LVCH16245AEVK
(935271944557)
Obsolete LVCH16245A Standard Procedure Standard Procedure
74LVCH16245AEV/G:5
(935281128551)
Obsolete LVCH16245A Standard Procedure Standard Procedure
74LVCH16245AEV/G,5
(935281128557)
Obsolete LVCH16245A Standard Procedure Standard Procedure

環(huán)境信息

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74LVCH16245AEV 74LVCH16245AEV,118 74LVCH16245AEV rhf
74LVCH16245AEV 74LVCH16245AEV,151 74LVCH16245AEV rhf
74LVCH16245AEV 74LVCH16245AEV,157 74LVCH16245AEV rhf
74LVCH16245AEV 74LVCH16245AEVY 74LVCH16245AEV    
74LVCH16245AEV 74LVCH16245AEV,551 74LVCH16245AEV rhf
74LVCH16245AEV 74LVCH16245AEVK 74LVCH16245AEV    
74LVCH16245AEV 74LVCH16245AEV/G:5 74LVCH16245AEV rohs rhf rhf
74LVCH16245AEV 74LVCH16245AEV/G,5 74LVCH16245AEV rohs rhf rhf
品質(zhì)及可靠性免責聲明

文檔 (3)

文件名稱 標題 類型 日期
74LVC_LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state Data sheet 2024-04-23
AN11009 Pin FMEA for LVC family Application note 2019-01-09
lvch16245a lvch16245a IBIS model IBIS model 2013-04-09

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模型

文件名稱 標題 類型 日期
lvch16245a lvch16245a IBIS model IBIS model 2013-04-09

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.