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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74LVCH16373ADGV-Q100

16-bit D-type transparent latch with 5 V tolerant inputs?/?outputs; 3-state

The 74LVC16373A-Q100 and 74LVCH16373A-Q100 are 16-bit D-type transparent latches with 3-state outputs. The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Bus hold on the data inputs eliminates the need for external pull?-?up resistors to hold unused inputs.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Overvoltage tolerant inputs to 5.5 V

  • Wide supply voltage range from 1.2 V to 3.6 V

  • CMOS low power dissipation

  • MULTIBYTE flow-through standard pinout architecture

  • Multiple low inductance supply pins for minimum noise and ground bounce

  • Direct interface with TTL levels

  • All data inputs have bus hold (74LVCH16373A-Q100 only)

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standards:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

參數類型

型號 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Ψth(j-top) (K/W) Rth(j-c) (K/W) Package name
74LVCH16373ADGV-Q100 1.2?-?3.6 TTL ± 24 3 low -40~125 82 2 37 TVSOP48

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

型號 可訂購的器件編號，（訂購碼(12NC)） 狀態 標示 封裝 外形圖 回流焊/波峰焊 包裝
74LVCH16373ADGV-Q100 74LVCH16373ADGV-QJ
(935690799118)		 Active 4LVCH16373A SOT480-1
TVSOP48
(SOT480-1) 		SOT480-1 SOT480-1_118

環境信息

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74LVCH16373ADGV-Q100 74LVCH16373ADGV-QJ 74LVCH16373ADGV-Q100 rohs rhf rhf
品質及可靠性免責聲明

文檔 (10)

文件名稱 標題 類型 日期
74LVC_LVCH16373A_Q100 16-bit D-type transparent latch with 5 V tolerant inputs?/?outputs; 3-state Data sheet 2024-04-23
AN11009 Pin FMEA for LVC family Application note 2019-01-09
SOT480-1 3D model for products with SOT480-1 package Design support 2020-01-22
lvch16373a lvch16373a IBIS model IBIS model 2013-04-09
Nexperia_document_leaflet_Logic_TVSOP48_16bitPortfolio_201903 Smaller-footprint 16-bit logic with advanced features Leaflet 2019-03-29
Nexperia_document_leaflet_Logic_TVSOP48_16bitPortfolio_201903 Smaller-footprint 16-bit logic with advanced features Leaflet 2019-03-29
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT480-1 plastic, thin shrink small outline package; 48 leads; 0.4 mm pitch; 9.7 mm x 4.4 mm x 1.1 mm body Package information 2022-06-22
SOT480-1_118 TVSOP48; Reel pack for SMD, 13"; Q1/T1 product orientation Packing information 2022-12-21
74LVCH16373ADGV-Q100_Nexperia_Product_Reliability 74LVCH16373ADGV-Q100 Nexperia Product Reliability Quality document 2024-06-16

支持

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模型

文件名稱 標題 類型 日期
lvch16373a lvch16373a IBIS model IBIS model 2013-04-09
SOT480-1 3D model for products with SOT480-1 package Design support 2020-01-22

PCB Symbol, Footprint and 3D Model

Model Name 描述

訂購、定價與供貨

型號 Orderable part number Ordering code (12NC) 狀態 包裝 Packing Quantity 在線購買
74LVCH16373ADGV-Q100 74LVCH16373ADGV-QJ 935690799118 Active SOT480-1_118 2,500 訂單產品

樣品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購部件

型號 可訂購的器件編號 訂購代碼(12NC) 封裝 從經銷商處購買
74LVCH16373ADGV-Q100 74LVCH16373ADGV-QJ 935690799118 SOT480-1 訂單產品