可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74LVT16374ADGG | 74LVT16374ADGG,118 | 935203010118 | SOT362-1 | 訂單產(chǎn)品 |
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Click here for more information74LVT16374ADGG
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
The 74LVT16374A; 74LVTH16374A is a 16?-?bit edge?-?triggered D?-?type flip?-?flop with 3?-?state outputs. The device can be used as two 8?-?bit flip?-?flops or one 16?-?bit flip?-?flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8?-?bits. The flip?-?flops will store the state of their individual D?-?inputs that meet the set?-?up and hold time requirements on the LOW?-?to?-?HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high?-?impedance OFF?-?state. Operation of the nOE input does not affect the state of the flip?-?flops.
Features and benefits
16-bit edge-triggered flip-flop
3-state buffers
Output capability: +64 mA and -32 mA
Wide supply voltage range from 2.7 to 3.6 V
Overvoltage tolerant inputs to 5.5 V
BiCMOS high speed and output drive
Direct interface with TTL levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs. (74LVTH16374A only)
Live insertion and extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to 85 °C
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|
| 74LVT16374ADGG | 2.7?-?3.6 | TTL | -32/+64 | 3.0 | 150 | medium | -40~85 | TSSOP48 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVT16374ADGG | 74LVT16374ADGG,118 (935203010118) |
Active | LVT16374A LVT16374A Standard Procedure Standard Procedure |
TSSOP48 (SOT362-1) |
SOT362-1 |
SSOP-TSSOP-VSO-WAVE
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SOT362-1_118 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVT16374ADGG | 74LVT16374ADGG,118 | 74LVT16374ADGG |
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Series
文檔 (9)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVT_LVTH16374A | 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state | Data sheet | 2024-07-08 |
| SOT362-1 | 3D model for products with SOT362-1 package | Design support | 2020-01-22 |
| lvt16374a | lvt16374a IBIS model | IBIS model | 2013-04-09 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP48_SOT362-1_mk | plastic, thin shrink small outline package; 48 leads; 0.5 mm pitch; 12.8 mm x 6.1 mm x 1.2 mm body | Marcom graphics | 2017-01-28 |
| SOT362-1 | plastic thin shrink small outline package; 48 leads; body width 6.1 mm | Package information | 2024-01-05 |
| SOT362-1_118 | TSSOP48; Reel pack for SMD, 13''; Q1/T1 product orientation | Packing information | 2020-04-21 |
| 74LVT16374ADGG_Nexperia_Product_Reliability | 74LVT16374ADGG Nexperia Product Reliability | Quality document | 2024-06-16 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
支持
如果您需要設(shè)計/技術(shù)支持，請告知我們并填寫 應(yīng)答表 我們會盡快回復(fù)您。
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
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訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74LVT16374ADGG | 74LVT16374ADGG,118 | 935203010118 | Active | SOT362-1_118 | 2,000 | 訂單產(chǎn)品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74LVT16374ADGG
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
從安世半導(dǎo)體購買
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