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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

NPIC6C595PW

Power logic 8-bit shift register; open-drain outputs

The NPIC6C595 is an 8?-?bit serial?-?in/serial or parallel?-?out shift register with a storage register and open?-?drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset input (MR). A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW?-?to?-?HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW?-?to?-?HIGH transition of the STCP input and to the Q7S output on a LOW?-?to?-?HIGH transition of the SHCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. Data in the storage register drives the gate of the output extended?-?drain NMOS transistor whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high?-?impedance OFF?-?state. Operation of the OE input does not affect the state of the registers. The open?-?drain outputs are 33 V?/?100 mA continuous current extended?-?drain NMOS transistors designed for use in systems that require moderate load power such as LEDs.

Integrated voltage clamps in the outputs provide protection against inductive transients. This feature makes the device suitable for power driver applications such as relay, solenoids and other low?-?current or medium?-?voltage loads.

此產品已停產

Features and benefits

  • Specified from -40 °C to +125 °C

  • Low RDSon

  • Eight Power EDNMOS transistor outputs of 100 mA continuous current

  • 250 mA current limit capability

  • Output clamping voltage 33 V

  • 30 mJ avalanche energy capability

  • All registers cleared with single input

  • Low power consumption

  • ESD protection:

    • HBM JDS-001 Class 2 exceeds 2500 V

    • CDM JESD22-C101E exceeds 1000 V

Applications

  • LED sign

  • Graphic status panel

  • Fault status indicator

參數類型

型號 Package name
NPIC6C595PW TSSOP16

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號，（訂購碼(12NC)） 狀態 標示 封裝 外形圖 回流焊/波峰焊 包裝
NPIC6C595PW NPIC6C595PW,118
(935297271118)		 Withdrawn / End-of-life IC6C595 SOT403-1
TSSOP16
(SOT403-1) 		SOT403-1 SSOP-TSSOP-VSO-WAVE
SOT403-1_118

環境信息

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
NPIC6C595PW NPIC6C595PW,118 NPIC6C595PW rohs rhf rhf
品質及可靠性免責聲明

文檔 (10)

文件名稱 標題 類型 日期
NPIC6C595 Power logic 8-bit shift register; open-drain outputs Data sheet 2020-06-09
AN11537 Pin FMEA for NPIC Family Application note 2019-10-07
SOT403-1 3D model for products with SOT403-1 package Design support 2020-01-22
npic6c595 NPIC6C595 IBIS model IBIS model 2016-05-30
Nexperia_document_leaflet_Logic_NPIC_ShiftRegisters_201906 NPIC Logic Shift Registers Leaflet 2019-07-12
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
TSSOP16_SOT403-1_mk plastic, thin shrink small outline package; 16 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body Marcom graphics 2017-01-28
SOT403-1 plastic, thin shrink small outline package; 16 leads; 5 mm x 4.4 mm x 1.2 mm body Package information 2023-11-08
NPIC6C595PW_Nexperia_Product_Reliability NPIC6C595PW Nexperia Product Reliability Quality document 2022-05-04
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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模型

文件名稱 標題 類型 日期
npic6c595 NPIC6C595 IBIS model IBIS model 2016-05-30
SOT403-1 3D model for products with SOT403-1 package Design support 2020-01-22

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.