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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)
BUK7K17-60E

BUK7K17-60E

Dual N-channel 60 V, 14 mΩ standard level MOSFET

1. General description

Dual standard level N-channel MOSFET in an LFPAK56D (Dual Power-SO8) package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use in high performance automotive applications.

2. Features and benefits

  • Dual MOSFET

  • Q101 compliant

  • Repetitive avalanche rated

  • Suitable for thermally demanding environments due to 175 °C rating

  • True standard level gate with VGS(th) of greater than 1 V at 175 °C

3. Applications

  • 12 V Automotive systems

  • Motors, lamps and solenoid control

  • Transmission control

  • Ultra high performance power switching

4. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit
The drain-source voltage rating is the voltage that a MOSFET can safely sustain between its drain and source in an OFF-state.
VDS
 drain-source voltage
Tj ≥ 25.0 °C;
Tj ≤ 175.0 °C
60 V
The drain-source current refers to the maximum continuous current through the MOSFET channel in an ON-state.
ID
 drain current
VGS = 10.0 V;
-55 °C
175 °C
Continuous current is limited by package
41 A
The total power dissipation capability given against temperature range between mounting base temperature and the max junction temperature.
Ptot
 total power dissipation
-55 °C
175 °C
 53 W
Static characteristics FET1 and FET2
The resistance of the device in the on-state under the conditions described. Drain-source on resistance varies greatly with both junction temperature and the gate-source voltage (VGS).
RDSon
 drain-source on-state resistance
2.8 V
15 V
1 A
30 A
-55 °C
175 °C
 8.55 mΩ
Dynamic characteristics FET1 and FET2
The gate-drain charge is a part of the switching transition. It is responsible for how long the switching transition is held at plateu region.
QGD
 gate-drain charge
1 A
30 A
5 V
55 V
VGS = 20.0 V;
Tj = 25.0 °C
6.81 nC

5. Pinning information

Pin

Symbol

Description

Simplified outline

Graphic symbol

1

S1

source1


LFPAK56D; Dual LFPAK (SOT1205)

2

G1

gate1

3

S2

source2

4

G2

gate2

5

D2

drain2

6

D2

drain2

7

D1

drain1

8

D1

drain1

6. Ordering information

Type number

Package

Name

Description

Version

BUK7K17-60E

LFPAK56D; Dual LFPAK

plastic, single ended surface mounted package (LFPAK56D); 8 leads

SOT1205

7. Marking

Type number

Marking code

BUK7K17-60E

 
71760E

8. Limiting values

Symbol Parameter Conditions Min Typ Max Unit
The drain-source voltage rating is the voltage that a MOSFET can safely sustain between its drain and source in an OFF-state.
VDS
 drain-source voltage
Tj ≥ 25.0 °C;
Tj ≤ 175.0 °C
60 V
The drain-gate voltage rating usually shares the same capability as drain-source voltage.
VDGR
 drain-gate voltage
RGS = 20.0 kΩ
60 V
The gate-source voltage rating of the MOSFET refering to the maximum voltage that can be applied across gate-source.
VGS
 gate-source voltage
Tj ≤ 175.0 °C;
DC
-20 20 V
The total power dissipation capability given against temperature range between mounting base temperature and the max junction temperature.
Ptot
 total power dissipation
-55 °C
175 °C
 53 W
The drain-source current refers to the maximum continuous current through the MOSFET channel in an ON-state.
ID
 drain current
-55 °C
175 °C
VGS = 10.0 V;
Continuous current is limited by package
41 A
The pulsed drain current for which max value is given at 10us.
IDM
 peak drain current
Tmb = 25.0 °C;
pulsed;
tp ≤ 10.0 µs
164 A
The storage temperature is the temperature range in which the device can be stored without affecting its reliability.
Tstg
 storage temperature -55 175 °C
The junction temperature of the device refers to the capability of the silicon die of the MOSFET. Junction temperature is given as a range of operational temperatures of the MOSFET.
Tj
 junction temperature -55 175 °C
Source-drain diode FET1 and FET2
The source-drain current is the maximum continous current though the MOSFET body diode (with the MOSFET in OFF-state)
IS
 source current
Tmb = 25.0 °C;
Continuous current is limited by package
30 A
The pulse current through the body diode of the MOSFET.
ISM
 peak source current
pulsed;
tp ≤ 10.0 µs;
Tmb = 25.0 °C
164 A
Avalanche ruggedness FET1 and FET2
The single event Avalanche Energy capability of MOSFET at the conditions given.
EDS(AL)S
 non-repetitive drain-source avalanche energy
ID = 30.0 A;
Vsup ≤ 60.0 V;
VGS = 10.0 V;
Tj(init) = 25.0 °C;
Refer to application note AN10273 for further information;
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C
55 mJ


P d e r = P t o t P t o t   ( 25   ° C ) × 100 %
Figure 1. Normalized total power dissipation as a function of mounting base temperature
ID (A)
Tmb (°C)

(1) Capped at 30 A due to package

VGS ≥ 10 V

Figure 2. Continuous drain current as a function of mounting base temperature


Tmb = 25 °C; IDM is a single pulse

Figure 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage


(1) Tj (init) = 25 °C; (2) Tj (init) = 150 °C; (3) Repetitive Avalanche

Figure 4. Avalanche rating; avalanche current as a function of avalanche time

9. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit
The thermal resistance between the silicon junction and the MOSFET mounting base. Mounting base is sometimes referred to as case in other datasheets.
Rth(j-mb)
 thermal resistance from junction to mounting base 2.84 K/W
Rth(j-a)
 thermal resistance from junction to ambient
Minimum footprint; mounted on a printed circuit board
95 K/W


Figure 1. Transient thermal impedance from junction to mounting base as a function of pulse duration

10. Characteristics

Symbol Parameter Conditions Min Typ Max Unit
Static characteristics FET1 and FET2
The minimum voltage the device is guaranteed to block between the drain and source terminals in the OFF-state.
V(BR)DSS
 drain-source breakdown voltage
ID = 250.0 µA;
VGS = 0.0 V;
-55 °C
175 °C
 62.8 V
The gate-source threshold voltage needed for MOSFETs to conduct a certain drain-current at a specific junction temperature. It is temperature dependent and at higher temperatures the threshold value is lower.
VGS(th)
 gate-source threshold voltage
ID = 1.0 mA;
VDS = VGS;
-55 °C
175 °C
 3.17 V
The drain-source leakage current when the MOSFET is in OFF-state. It is temperature dependent and gets higher at higher temperatures.
IDSS
 drain leakage current
5 V
60 V
VGS = 0.0 V;
-55 °C
175 °C
 0.03 µA
The gate-source leakage current normally in nA range. It is temperature dependent and gets higher at higher temperatures.
IGSS
 gate leakage current
VGS = -20.0 V;
VDS = 0.0 V;
Tj = 25.0 °C
2 100 nA
The resistance of the device in the on-state under the conditions described. Drain-source on resistance varies greatly with both junction temperature and the gate-source voltage (VGS).
RDSon
 drain-source on-state resistance
2.8 V
15 V
1 A
30 A
-55 °C
175 °C
 8.55 mΩ
Dynamic characteristics FET1 and FET2
The total gate charge of the MOSFET. Covering the full switching transition showing turn-on threshold, linear mode, and fully enhanced stages.
QG(tot)
 total gate charge
1 A
30 A
5 V
55 V
0 V
15 V
Tj = 25.0 °C
20.4 nC
The gate-source charge parameter is a part of the switching transition. It is normally used to determine turn-on time.
QGS
 gate-source charge
1 A
30 A
5 V
55 V
VGS = 10.0 V;
Tj = 25.0 °C
4.81 nC
The gate-drain charge is a part of the switching transition. It is responsible for how long the switching transition is held at plateu region.
QGD
 gate-drain charge
1 A
30 A
5 V
55 V
VGS = 20.0 V;
Tj = 25.0 °C
6.81 nC
The capacitance between the gate and the other two terminals (source and drain). The parameter is voltage dependent.
Ciss
 input capacitance
VGS = 0.0 V;
0 V
55 V
f = 1.0 MHz;
Tj = 25.0 °C
1058 pF
The capacitance between the drain and the other two terminals (gate and source). The parameter is voltage dependent.
Coss
 output capacitance
VGS = 0.0 V;
0 V
55 V
f = 1.0 MHz;
Tj = 25.0 °C
160 pF
The capacitance between the drain and the gate. The parameter is voltage dependent.
Crss
 reverse transfer capacitance
VGS = 0.0 V;
0 V
55 V
f = 1.0 MHz;
Tj = 25.0 °C
108 pF
td(on)
 turn-on delay time
10 V
55 V
RL = 5.0 Ω;
VGS = 10.0 V;
5 Ω
30 Ω
Tj = 25.0 °C;
5 A
30 A
 7.37 ns
tr
 rise time
10 V
55 V
RL = 5.0 Ω;
VGS = 10.0 V;
5 Ω
30 Ω
Tj = 25.0 °C;
5 A
30 A
 7.32 ns
td(off)
 turn-off delay time
10 V
55 V
RL = 5.0 Ω;
VGS = 10.0 V;
5 Ω
30 Ω
Tj = 25.0 °C;
5 A
30 A
 13.5 ns
tf
 fall time
10 V
55 V
RL = 5.0 Ω;
VGS = 10.0 V;
5 Ω
30 Ω
Tj = 25.0 °C;
5 A
30 A
 9.78 ns
Source-drain diode FET1 and FET2
The forward voltage of the MOSFET body diode under the conditions described.
VSD
 source-drain voltage
5 A
164 A
VGS = 0.0 V;
-55 °C
175 °C
 0.82 V
The time taken to recover the charge from the anti-parallel diode when it is switched from its conducting state to its reverse biased (diode) state. Reverse recovery time is related to switching performance.
trr
 reverse recovery time
IS = 10.0 A;
dIS/dt = -100.0 A/µs;
VGS = 0.0 V;
VDS = 30.0 V;
Tj = 25.0 °C
24.5 ns
The total amount of charge recovered from the anti-parallel diode when it is switched from its conducting state to its reverse biased (diode) state. Reverse recovery charge is related to switching performance.
Qr
 recovered charge
5 A
30 A
-1200 A/µs
-100 A/µs
VGS = 0.0 V;
VDS = 30.0 V;
Tj = 25.0 °C
14.2 nC


Tj = 25 °C; ID = 10 A

Figure 1. Drain-source on-state resistance as a function of gate-source voltage; typical values


VDS = 10 V

Figure 2. Transfer characteristics; drain current as a function of gate-source voltage; typical values


Tj = 25 °C; tp = 300 μs

Figure 3. Output characteristics; drain current as a function of drain-source voltage; typical values


Tj = 25 °C; VDS = 5 V

Figure 4. Sub-threshold drain current as a function of gate-source voltage


ID = 1 mA; VDS = VGS

Figure 5. Gate-source threshold voltage as a function of junction temperature


Tj = 25 °C; tp = 300 μs

Figure 6. Drain-source on-state resistance as a function of drain current; typical values


a = R D S o n R D S o n ⁢     ( 25 ° C )
Figure 7. Normalized drain-source on-state resistance factor as a function of junction temperature


Figure 8. Gate charge waveform definitions


Tj = 25 °C; ID = 10 A

Figure 9. Gate-source voltage as a function of gate charge; typical values


VGS = 0 V; f = 1 MHz

Figure 10. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values


VGS = 0 V

Figure 11. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values

11. Package outline

Figure 1. Package outline LFPAK56D; Dual LFPAK (SOT1205)

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