74ALVCH16821DGG

20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state

The 74ALVCH16821 has two 10?-?bit, edge triggered registers, with each register coupled to a 3?-?state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable nOE control gates.

Each register is fully edge triggered. The state of each nDn input, one set?-?up time before the LOW?-?to?-?HIGH clock transition, is transferred to the corresponding flip?-?flop’s nQn output.

When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip?-?flops.

The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull?-?up or pull?-?down resistors.

Features and benefits

Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTE? flow-through standard pin-out architecture
Low inductance multiple V_CC and GND pins for minimum noise and ground bounce
Output drive capability 50 ? transmission lines at 85°C
All data inputs have bushold
Complies with JEDEC standard no. 8-1A
Complies with JEDEC standards:
- JESD8-5 (2.3 V to 2.7 V)
- JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C

參數(shù)類型

型號	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Power dissipation considerations	T_amb (°C)	Package name
74ALVCH16821DGG	1.2?-?3.6	TTL	± 24	2.5	350	low	-40~85	TSSOP56

封裝

型號	可訂購的器件編號，（訂購碼(12NC)）	狀態(tài)	標(biāo)示	封裝	外形圖	回流焊/波峰焊	包裝
74ALVCH16821DGG	74ALVCH16821DGG,11 (935259010118)	Active	ALVCH16821	TSSOP56 (SOT364-1)	SOT364-1	SSOP-TSSOP-VSO-WAVE	SOT364-1_118

環(huán)境信息

型號	可訂購的器件編號	化學(xué)成分	RoHS	RHF指示符
74ALVCH16821DGG	74ALVCH16821DGG,11	74ALVCH16821DGG

品質(zhì)及可靠性免責(zé)聲明

Series

文檔 (8)

文件名稱	標(biāo)題	類型	日期
74ALVCH16821	20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state	Data sheet	2024-07-09
SOT364-1	3D model for products with SOT364-1 package	Design support	2020-01-22
alvch16821	alvch16821 IBIS model	IBIS model	2013-04-08
Nexperia_package_poster	Nexperia package poster	Leaflet	2020-05-15
SOT364-1	plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body	Package information	2022-06-23
SOT364-1_118	TSSOP56; Reel pack for SMD, 13"; Q1/T1 product orientation	Packing information	2020-04-21
74ALVCH16821DGG_Nexperia_Product_Reliability	74ALVCH16821DGG Nexperia Product Reliability	Quality document	2024-06-16
SSOP-TSSOP-VSO-WAVE	Footprint for wave soldering	Wave soldering	2009-10-08

支持

如果您需要設(shè)計(jì)/技術(shù)支持，請告知我們并填寫應(yīng)答表我們會盡快回復(fù)您。

模型

文件名稱	標(biāo)題	類型	日期
alvch16821	alvch16821 IBIS model	IBIS model	2013-04-08
SOT364-1	3D model for products with SOT364-1 package	Design support	2020-01-22

訂購、定價(jià)與供貨

型號	Orderable part number	Ordering code (12NC)	狀態(tài)	包裝	Packing Quantity	在線購買
74ALVCH16821DGG	74ALVCH16821DGG,11	935259010118	Active	SOT364-1_118	2,000	訂單產(chǎn)品

樣品

作為 Nexperia 的客戶，您可以通過我們的銷售機(jī)構(gòu)訂購樣品。

如果您沒有 Nexperia 的直接賬戶，我們的全球和地區(qū)分銷商網(wǎng)絡(luò)可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表。

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

交互式數(shù)據(jù)手冊