可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經銷商處購買 |
|---|---|---|---|---|
| 74ALVT16823DGG | 74ALVT16823DGG,118 | 935261019118 | SOT364-1 | 訂單產品 |
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Click here for more information74ALVT16823DGG
18-bit bus-interface D-type flip-flop with reset and enable; 3?-?state
The 74ALVT16823 is an 18??-??bit positive?-?edge triggered D?-?type flip?-?flop with 3?-?state outputs, reset and enable.
The device can be used as two 9?-?bit flip?-?flops or one 18?-?bit flip?-?flop. The device features clock (nCP), clock enable (nCE), master reset (nMR) and output enable (nOE, inputs each controlling 9?-?bits. When nCE is LOW, the flip?-?flops will store the state of their individual D?-?inputs that meet the set?-?up and hold time requirements on the LOW?-?to?-?HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high?-?impedance OFF?-?state. Operation of the nOE input does not affect the state of the flip?-?flops. A LOW on nMR will reset the flip?-?flops LOW. Bus hold data inputs eliminate the need for external pull?-?up resistors to define unused inputs
Features and benefits
Wide supply voltage range from 2.3 V to 3.6 V
Overvoltage tolerant inputs to 5.5 V
BiCMOS high speed and output drive
Direct interface with TTL levels
Bus hold on data inputs
Power-up 3-state
IOFF circuitry provides partial Power-down mode operation
Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors
Live insertion and extraction permitted
Power-up reset
No bus current loading when output is tied to 5 V bus
Output capability: +64 mA to -32 mA
Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to 85 °C
參數類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|
| 74ALVT16823DGG | 2.3?-?3.6 | TTL | -32/+64 | 1.9 | 250 | medium | -40~85 | TSSOP56 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態 | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74ALVT16823DGG | 74ALVT16823DGG,118 (935261019118) |
Active | ALVT16823 |
TSSOP56 (SOT364-1) |
SOT364-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT364-1_118 |
Series
文檔 (9)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74ALVT16823 | 18-bit bus-interface D-type flip-flop with reset and enable; 3?-?state | Data sheet | 2024-06-25 |
| SOT364-1 | 3D model for products with SOT364-1 package | Design support | 2020-01-22 |
| alvt16823 | alvt16823 IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SOT364-1 | plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body | Package information | 2022-06-23 |
| SOT364-1_118 | TSSOP56; Reel pack for SMD, 13"; Q1/T1 product orientation | Packing information | 2020-04-21 |
| 74ALVT16823DGG_Nexperia_Product_Reliability | 74ALVT16823DGG Nexperia Product Reliability | Quality document | 2024-06-16 |
| alvt16 | alvt16 Spice model | SPICE model | 2013-05-07 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
支持
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訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態 | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74ALVT16823DGG | 74ALVT16823DGG,118 | 935261019118 | Active | SOT364-1_118 | 2,000 | 訂單產品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74ALVT16823DGG
18-bit bus-interface D-type flip-flop with reset and enable; 3?-?state
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