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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74LVT16374ADL

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

The 74LVT16374A; 74LVTH16374A is a 16?-?bit edge?-?triggered D?-?type flip?-?flop with 3?-?state outputs. The device can be used as two 8?-?bit flip?-?flops or one 16?-?bit flip?-?flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8?-?bits. The flip?-?flops will store the state of their individual D?-?inputs that meet the set?-?up and hold time requirements on the LOW?-?to?-?HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high?-?impedance OFF?-?state. Operation of the nOE input does not affect the state of the flip?-?flops.

此產品已停產

Features and benefits

  • 16-bit edge-triggered flip-flop

  • 3-state buffers

  • Output capability: +64 mA and -32 mA

  • Wide supply voltage range from 2.7 to 3.6 V

  • Overvoltage tolerant inputs to 5.5 V

  • BiCMOS high speed and output drive

  • Direct interface with TTL levels

  • Input and output interface capability to systems at 5 V supply

  • Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs. (74LVTH16374A only)

  • Live insertion and extraction permitted

  • Power-up reset

  • Power-up 3-state

  • No bus current loading when output is tied to 5 V bus

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

  • Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to 85 °C

參數類型

型號 Package name
74LVT16374ADL SSOP48

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態 標示 封裝 外形圖 回流焊/波峰焊 包裝
74LVT16374ADL 74LVT16374ADL,112
(935184410112)
Obsolete LVT16374A LVT16374A Standard Procedure Standard Procedure SOT370-1
SSOP48
(SOT370-1)
SOT370-1 SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE
暫無信息
74LVT16374ADL,118
(935184410118)
Obsolete LVT16374A LVT16374A Standard Procedure Standard Procedure SOT370-1_118

環境信息

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74LVT16374ADL 74LVT16374ADL,112 74LVT16374ADL rohs rhf rhf
74LVT16374ADL 74LVT16374ADL,118 74LVT16374ADL rohs rhf rhf
品質及可靠性免責聲明

文檔 (6)

文件名稱 標題 類型 日期
74LVT_LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Data sheet 2024-07-08
lvt16374a lvt16374a IBIS model IBIS model 2013-04-09
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT370-1 plastic, shrink small outline package; 48 leads; 0.635 mm pitch; 15.9 mm x 7.5 mm x 2.8 mm body Package information 2020-04-21
SSOP-TSSOP-VSO-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

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模型

文件名稱 標題 類型 日期
lvt16374a lvt16374a IBIS model IBIS model 2013-04-09

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.