74ALVCH16843DGG

18-bit bus-interface D-type latch; 3-State

The 74ALVCH16843 has two 9–bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE), clear (nCLR), preset (nPRE) and output enable (nOE) control gates.

When nOE is LOW, the data in the registers appear at the outputs. When nOE is HIGH, the outputs are in the high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops.

The 74ALVCH16843 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

Features and benefits

Wide supply voltage range of 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Current drive ±24 mA at V_CC = 3.0 V.
MULTIBYTE? flow-through standard pin-out architecture
Low inductance multiple V_CC and GND pins for minimize noise and ground bounce
All data inputs have bushold
Output drive capability 50 Ω transmission lines at 85 °C
3-state non-inverting outputs for bus oriented applications
Complies with JEDEC standards:
- JESD8-5 (2.3 V to 2.7 V)
- JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C

參數(shù)類型

型號	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	Package name
74ALVCH16843DGG	1.2?-?3.6	LVTTL	± 24	2.1	low	-40~85	93	21	TSSOP56

封裝

型號	可訂購的器件編號，（訂購碼(12NC)）	狀態(tài)	標示	封裝	外形圖	回流焊/波峰焊	包裝
74ALVCH16843DGG	74ALVCH16843DGG,11 (935259110118)	Active	ALVCH16843	TSSOP56 (SOT364-1)	SOT364-1	SSOP-TSSOP-VSO-WAVE	SOT364-1_118

環(huán)境信息

型號	可訂購的器件編號	化學成分	RoHS	RHF指示符
74ALVCH16843DGG	74ALVCH16843DGG,11	74ALVCH16843DGG

品質(zhì)及可靠性免責聲明

Series

文檔 (8)

文件名稱	標題	類型	日期
74ALVCH16843	18-bit bus-interface D-type latch; 3-State	Data sheet	2024-07-10
SOT364-1	3D model for products with SOT364-1 package	Design support	2020-01-22
alvch16843	alvch16843 IBIS model	IBIS model	2013-04-08
Nexperia_package_poster	Nexperia package poster	Leaflet	2020-05-15
SOT364-1	plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body	Package information	2022-06-23
SOT364-1_118	TSSOP56; Reel pack for SMD, 13"; Q1/T1 product orientation	Packing information	2020-04-21
74ALVCH16843DGG_Nexperia_Product_Reliability	74ALVCH16843DGG Nexperia Product Reliability	Quality document	2024-06-16
SSOP-TSSOP-VSO-WAVE	Footprint for wave soldering	Wave soldering	2009-10-08

支持

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模型

文件名稱	標題	類型	日期
alvch16843	alvch16843 IBIS model	IBIS model	2013-04-08
SOT364-1	3D model for products with SOT364-1 package	Design support	2020-01-22

訂購、定價與供貨

型號	Orderable part number	Ordering code (12NC)	狀態(tài)	包裝	Packing Quantity	在線購買
74ALVCH16843DGG	74ALVCH16843DGG,11	935259110118	Active	SOT364-1_118	2,000	訂單產(chǎn)品

樣品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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